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MIPI D-PHY Transmitter - Designed for TSMC 40nmLP
The MXL-DPHY-CSI2-TX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI master and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for camera interface applications (CSI2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI master and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for camera interface applications (CSI2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
特色
- Consists of 1 Clock lane and 4 Data lanes
- Complies with MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.5Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed De-Serializers included
- Low power dissipation
可交付内容
- Datasheet
- GDSII and LVS Netlist
- Integration Guideline
- Timing Model and Behavioral Model
- One year support
- Platform optional
应用
- Mobile
- Automotive
- IoT
- Consumer Electronics
- VR
- AR
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