You are here:
MIPI D-PHY Receiver IP(Silicon Proven in TSMC 22ULP)
The MIPI D-PHY Analog RX IP Core is fully compliant to the D-PHY specification version 1.2. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DS!) protocols. It is a RX PHY with one clock lane and 4 data lanes. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. Internal termination resistor with auto-calibration. DSI PHY T22ULP is a MIPI DSI PHY (MIPI RX DPHY) Includes a PLL, a Clock Lane and four Data Lane also DSIPHYT22ULP can be used as a 5V tolerance GPIO bank.
查看 MIPI D-PHY Receiver IP(Silicon Proven in TSMC 22ULP) 详细介绍：
- 查看 MIPI D-PHY Receiver IP(Silicon Proven in TSMC 22ULP) 完整数据手册
- 联系 MIPI D-PHY Receiver IP(Silicon Proven in TSMC 22ULP) 供应商
Block Diagram of the MIPI D-PHY Receiver IP(Silicon Proven in TSMC 22ULP)
MIPI DPHY Rx IP
- MIPI D-PHY CSI-2 RX+ 1.5Gbps for Automotive Applications
- MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables
- MIPI C-PHY/D-PHY Combo IP DSI RX in TSMC22ULP
- MIPI C-PHY/D-PHY Combo IP 4.5Gsps/4.5Gbps in TSMC N7
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Globalfoundries 12nm MIPI D-PHY V1.2@2.5GHz