The MIPI D-PHY Analog RX IP Core is fully compliant to the D-PHY specification version 1.2. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DS!) protocols. It is a RX PHY with one clock lane and 4 data lanes. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. Internal termination resistor with auto-calibration. DSI PHY T22ULP is a MIPI DSI PHY (MIPI RX DPHY) Includes a PLL, a Clock Lane and four Data Lane also DSIPHYT22ULP can be used as a 5V tolerance GPIO bank.