USB Type-C 40 Gb/s Multi-Protocol Switch and Bi-Directional Bit-Level Retimer
You are here:
MIPI D-PHY Receiver in TSMC 40nm LP
The MXL-PHY-CSI2-RX+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY.
The IP is configured as a MIPI slave optimized for camera interface applications (CSI2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI slave optimized for camera interface applications (CSI2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
特色
- Consists of 1 Clock lane and 2 Data lanes
- Supports the MIPI Standard 1.1 for D-PHYSM
- Supports both high speed and low-power modes
- 80 Mbps to 1.5Gbps data rate in high speed mode
- 20 Mbps data rate in low-power mode
- High Speed Deserializers included
- Low power dissipation
- Loopback testability support
可交付内容
- Datasheet
- GDSII and LVS Netlist
- Integration Guideline
- Timing Model and Behavioral Model
- RTL
- One year support
应用
- Automotive
- Mobile
- IoT
- Consumer Electronics
- VR
- AR
查看 MIPI D-PHY Receiver in TSMC 40nm LP 详细介绍：
- 查看 MIPI D-PHY Receiver in TSMC 40nm LP 完整数据手册
- 联系 MIPI D-PHY Receiver in TSMC 40nm LP 供应商