Our MIPI-D-PHY IP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Standard for D-PHY.To address the challenges of huge demand for advanced multimedia features are pushing device manufacturers to integrate more advanced peripherals such as multi-megapixel cameras and larger screens., the Mobile Industry Processor Interface (MIPI Alliance defines and promotes open interface specifications, such as the Camera Serial Interface (CSI-2), Display Serial Interface (DSI), which all use the MIPI D-PHY.
The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions.Our D-PHY provides a point to point connection between master and slave or host and device that comply with a relevant MIPI standard. The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.The D-PHY link supports a high speed (HS) mode for fast data traffic and a low power (LP) mode for control transactions.The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
- Supports standard PHY transceiver and Protocol Interface(PPI) interface compliant to MIPI Specification
- Compliant with the MIPI D-PHY specification, v1.2
- Supports both high speed and low-power modes
- High Speed Serializer and De-Serializer included
- Master, slave, Tx and Rx-only configurations
- Attachable PLL for master applications
- Clock lane supports unidirectional communication
- Supports High speed mode in Forward communication
- SCAN and loopback BIST modes
- Flexible input clock reference
- Supports error detection mechanism for sequence errors and contentions
- Shutdown mode
- Fully integrated hard macro
- Silicon-proven, robust design available in advanced process technologies
- Extensive access to internal programmability registers
- Available in various foundry processes
- Can be ported to other processes.
- Provides a high-reliability, high-speed differential interface, reducing line count and minimizing cable wires and EMI shielding requirements.
- Data Sheet with Specifications
- GDSII Layout Database
- LEF and .LIB file
- LVS Netlist
- Timing and Behavioural Model
- Integration Guidelines
- CSI-2 Host and CSI-2 Device for Camera
- DSI Device and Host for Mobile
- Consumer Electronics