28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
MIPI-D-PHY
The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions.Our D-PHY provides a point to point connection between master and slave or host and device that comply with a relevant MIPI standard. The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.The D-PHY link supports a high speed (HS) mode for fast data traffic and a low power (LP) mode for control transactions.The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
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