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MIPI D-PHY DSI TX (Transmitter) in TSMC 65LP
The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master and consists of 4 lanes: 1 Clock lane and 3 data lanes, which makes it suitable for Display Interface Applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
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Block Diagram of the MIPI D-PHY DSI TX (Transmitter) in TSMC 65LP
MIPI D-PHY Transmitter IP
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