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MIPI D-PHY DSI RX (Receiver) in TSMC 110G
The MXL-DPHY-DSI-RX-T-110G is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave with maximum of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for
High-Speed Data traffic while low power functions are mostly used for control.
High-Speed Data traffic while low power functions are mostly used for control.
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