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MIPI D-PHY, CSI-2 TX+ for TSMC40ULP
The MXL-D-PHY-CSI-TX+-T-40ULP is a high-frequency, low-power, low-cost, source synchronous,physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1.
The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in system testing while minimizing area and leakage power.
The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in system testing while minimizing area and leakage power.
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Block Diagram of the MIPI D-PHY, CSI-2 TX+ for TSMC40ULP
MIPI IP
- MIPI CSI-2 Controller Core V2
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm(
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Globalfoundries 12nm MIPI D-PHY V1.2@2.5GHz
- MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave