MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for camera interface applications (CSI2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
查看 MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP 详细介绍:
- 查看 MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP 完整数据手册
- 联系 MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP 供应商
Block Diagram of the MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP
MIPI D-PHY IP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)