MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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MIPI CSI-2 RX Controller
The Qualitas CSI-2 RX Controller offers high-speed serial connectivity between host processors and camera modules. Fully compliant with MIPI CSI-2 v2.0, this IP includes Receiver (Rx) capabilities over 4 D-PHY data lanes or 3 C-PHY data trios, with lane configurability to meet varying camera bandwidth requirements.
The IP supports all video pixel formats and provides optional video coordinate generation with Hsync, Vsync, and Video Data Enable (VDE). Additionally, it detects all packet-level and protocol decoding-level errors, ensuring data integrity.
Compliant with the CSE v1.0 specification, this IP includes functional safety features, making it ideal for automotive applications. It has undergone rigorous design verification through VIP function testing, ensuring reliable performance.
The IP supports all video pixel formats and provides optional video coordinate generation with Hsync, Vsync, and Video Data Enable (VDE). Additionally, it detects all packet-level and protocol decoding-level errors, ensuring data integrity.
Compliant with the CSE v1.0 specification, this IP includes functional safety features, making it ideal for automotive applications. It has undergone rigorous design verification through VIP function testing, ensuring reliable performance.
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Block Diagram of the MIPI CSI-2 RX Controller
