The MIPI CSI-2 Receiver IP is designed to provide MIPI CSI 1.01 compliant high speed serial connectivity for applications processors to corresponding camera modules in mobile platforms. Serial connectivity between this IP and an external the camera module’s CSI transmitter is implemented using 1 to 4 D-PHY lanes, depending on camera sensor resolutions and the resulting bandwidth needs. This IP connects to the D-PHY’s through the PPI interface.
Initial configuration of this IP and its associated D-PHY can be done through programmed IO over an AHB bus, however, other bus interfaces like AXI and OCP can be provided upon request.
This IP performs the data lane merging of image data received on PPI interface from D-PHY. It performs CRC and ECC checks to ensure the integrity of packet payload and header. Based on the user register settings, the IP either forwards or drops the erroneous packets. All forwarded packet payloads are then converted from byte to pixel format, decompressed and output to an external Image Signal Processor (ISP) of the applications processor’s graphics sub-system. All D-PHY Level errors, Packet Level errors and Protocol Decoding Level errors are communicated to the host from a status register.
- CSI-2 Combo Receiver Core features
- •Use of either D-PHY/C-PHY by user configuration
- •Different Configuration allowed for multiple use cases,
- •4-Lane/8-Lane D-PHY / 3-Lane C-PHY
- •Lane Configurability depending on the bandwidth requirements of the application, up to 8-lanes for DPHY and up to 3-lanes for C-PHY
- •High Speed (HS) receiver rates of 182Mbps to 5714Mbps per lane with C-PHY interface
- •High Speed (HS) receiver rates of 40Mbps to 2500Mbps per lane with D-PHY interface
- •Supports for Ultra Low Power Mode (ULPS)
- •Single (or) Optional Multi-Pixel mode interface to ISP. The multi-pixel mode is used in high bandwidth requirement applications to lower the ISP clock frequency requirement.
- •Optional Pixel Level Interface to ISP with HSYNC, VSYNC, DATA and DATA VALID
- •Streams the received pixels onto eight data channels(customizable) based on the channel configurability from ISP
- •Separate data channel for the short generic packets
- •Support for all packet level errors, Protocol Decoding Level errors<
- •Support for cut-though (or) store and forward mode. Cut-through mode makes use of shallow Memory for memory critical applications.
- •Optional support for Compressed data formats
- •Optional support for different error counting
- Pixel formats supported<br />
- • data type – RAW8, RAW10, RAW12, RAW14
- •YUV data type – YUV422-8bit, YUV422-10bit
- •RGB data type – RGB888, RGB666, RGB565, RGB555, RGB444
- •All user Defined data types / JPEG
- •Generic 8-bit long packet data types
- Host interface for register configuration and monitoring,
- •Used for programming both CSI-2 and PHY related registers. Reserved address space [0x00 – 0x0F] for the PHY related registers.
- •Optional support for the AHB/APB Interface
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
- Functionality ensured with comprehensive verification
- Product quality proven with silicon
- Premier direct support from Arasan IP core designers
- • Verilog HDL of the IP core
- • User guide
- • Synthesis scripts
- • Lint report
- • CDC report
- • Verilog test suite
- • Gate count estimation available upon request
Block Diagram of the MIPI CSI-2 Receiver v 1.3