The Media Local Bus Interface IP core complies with the latest MLB Specification version 4.2, and works with all MOST network generations - MOST25, MOST50, and MOST150. It supports a 3-pin single-ended MediaLB connection with up to 1024xFs, and a 6-pin differential connection with up to 4096xFs. The Media Local Bus Interface IP core provides internal buffering and support for up to 63 TX and RX channels.
The Media Local Bus Interface IP core supports implementation of the SMSC's Media Local Bus (MediaLB) inter-chip communication technology in Xilinx FPGA and an efficient transport of multimedia data through SMSC's Intelligent Network Interface Controllers (INICs) onto a Media Oriented System Transport (MOST) network. The MOST networks are infotainment backbones in many cars and de facto industry standard for automotive multimedia networking of high-bandwidth audio, video and control information or network data.
- Adds MOST® connectivity to Xilinx® FPGAs
- Licensed MediaLB® technology from SMSC®
- Compliant with the MLB Specification Version 4.2
- Supports 3-pin and 6-pin interface to INICs
- Supported transport methods: synchronous, asynchronous, control and isochronous
- Supports Xilinx Spartan®-6 FPGA family
- Enables an easy interfacing of next-generation Xilinx FPGA based automotive infotainment and driver assistance systems with the most popular automotive infotainment backbone - Media Oriented System Transport (MOST)
- encrypted VHDL
- reference FPGA design