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MCR DDR5 PHY
The INNOSILICON DDR Mixed-Signal MCR DDR5 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible MCR DDR5 DIMM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC MCR DIMM components in the market. The PHY components contain DDR specialized functional and utility high performance I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for DDR5 MCR DIMM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. Bus width of the MCR DDR5 PHY can be from 4 bit to 80 bit. INNOSILICON is happy to pre-assemble the PHY for our customer so that integration becomes extremely easy.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. Bus width of the MCR DDR5 PHY can be from 4 bit to 80 bit. INNOSILICON is happy to pre-assemble the PHY for our customer so that integration becomes extremely easy.
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