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Master/Slave Octal SPI Controller
Implements a controller for a single-, dual-, quad-, or octal-lane Serial Peripheral Interface (SPI) bus, which can operate either as a master or as a slave.
Designed to work with a wide variety of SPI-bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the most-significant bit position in a frame, serial clock phase and polarity are all software-programmable. In master mode the core can control up to 32 slaves. A software-controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose.
The SPI-MS provides access to is status and control registers, and to the SPI transfer data via a 32-bit APB slave interface. The core treats the APB and SPI clocks as asynchronous to each other, and implements a clean clock-domain crossing boundary. The core implements two configurable-depth FIFOs, one for the receiver and one for the transmitter path. To ease integration, an interrupt can be generated to indicate availability of a programmable amount of received data or availability to transmit a programmable amount of new data.
The SPI-MS core is rigorously verified, silicon-proven and available in RTL source or as a targeted FPGA netlist.
Designed to work with a wide variety of SPI-bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the most-significant bit position in a frame, serial clock phase and polarity are all software-programmable. In master mode the core can control up to 32 slaves. A software-controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose.
The SPI-MS provides access to is status and control registers, and to the SPI transfer data via a 32-bit APB slave interface. The core treats the APB and SPI clocks as asynchronous to each other, and implements a clean clock-domain crossing boundary. The core implements two configurable-depth FIFOs, one for the receiver and one for the transmitter path. To ease integration, an interrupt can be generated to indicate availability of a programmable amount of received data or availability to transmit a programmable amount of new data.
The SPI-MS core is rigorously verified, silicon-proven and available in RTL source or as a targeted FPGA netlist.
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Block Diagram of the Master/Slave Octal SPI Controller
Serial Peripheral Interface IP
- High Speed SPI AHB IP Core- Serial Peripheral Interface
- DO-254 AXI Serial Peripheral Interface (SPI) 1.00a
- Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support
- Serial Peripheral Interface – Master/Slave with single, dual, quad and octal SPI Bus support
- Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support
- eSPI & SPI Master / Slave Controller w/FIFO (APB, AHB, or AXI Bus)