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ManagedRedundantSwitch IP core (MRS) is a combination of SoCe HSR-PRPSwitch (HPS) and ManagedEthernetSwitch (MES) IP cores offering a redundant Ethernet switch capability. The MES module is a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements Store&Forward switching approach in order to ful l Ethernet standard policy regarding frame integrity checking each frame before forwarding them. On the other hand, the HPS module introduces HSR and PRP redundant capabilities in the ports that are required. HSR switching approach is Cut-Through.
Thus, the combination of MES and HPS offers the maximum performance and maximum compatibility with the standards.
MRS can be supported on the following Xilinx FPGA Families:
- 6-Series (Spartan, Virtex)
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
MRS is designed to be easily integrated in your FPGA designs by taking advantage of the new Xilinx Vivado Tool, that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.
Managed Redundant Switch
ManagedRedundantSwitch IP core (MRS) is a combination of SoCe HSR-PRPSwitch (HPS) and ManagedEthernetSwitch (MES) IP cores offering a redundant Ethernet switch capability. The MES module is a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements Store&Forward switching approach in order to ful l Ethernet standard policy regarding frame integrity checking each frame before forwarding them. On the other hand, the HPS module introduces HSR and PRP redundant capabilities in the ports that are required. HSR switching approach is Cut-Through.
Thus, the combination of MES and HPS offers the maximum performance and maximum compatibility with the standards.
MRS can be supported on the following Xilinx FPGA Families:
- 6-Series (Spartan, Virtex)
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
MRS is designed to be easily integrated in your FPGA designs by taking advantage of the new Xilinx Vivado Tool, that allows to use the IP Cores in a graphical user interface and configure IP parameters in an easy way.
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