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Majority voting combination rule core with parallel operation
So_ip_ecr_mv_p core can be used to implement several Majority Voting combination rules to calculate the ensemble classification of the instance based on the classifications supplied by the ensemble members. Ensemble members whose classifications are being combined can be of any type, decision trees, neural networks, support vector machines, or some other predictive models. Even more, the ensemble can be even composed from a mixture of different predictive models.
So_ip_ecr_mv_p core can be used to implement the following Majority Voting combination rule variants: unanimous voting, simple majority voting, and plurality voting.
So_ip_ecr_mv_p core should be used in conjunction with some ensemble evaluation module that is able to calculate the instance classifications for all ensemble members in parallel. Using these classifications, so_ip_ecr_mv_p core can calculate the combined classification of the current instance in parallel, to achieve the fastest classification speed.
So_ip_ecr_mv_p core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_ecr_mv_p design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_ecr_mv_p core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
So_ip_ecr_mv_p core can be used to implement the following Majority Voting combination rule variants: unanimous voting, simple majority voting, and plurality voting.
So_ip_ecr_mv_p core should be used in conjunction with some ensemble evaluation module that is able to calculate the instance classifications for all ensemble members in parallel. Using these classifications, so_ip_ecr_mv_p core can calculate the combined classification of the current instance in parallel, to achieve the fastest classification speed.
So_ip_ecr_mv_p core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_ecr_mv_p design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_ecr_mv_p core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
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