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Maestro Clock Generation Module [PLL], 10x smaller than existing solutions
Movellus' TrueDigital CGMs were purposely built for SoCs. Applications such as datacenter CPUs, AI accelerators, aerospace, and automotive require higher degrees of testability, reliability, and area-flexibility.
Maestro CGMs are all digital, leading to a 10-15x area reduction over analog PLLs. These footprint reductions allow architects to instantiate multiple CGMs within a core block, driving true DVFS capabilities.
The generation modules are also fully synthesizable which improves the coverage area (up to 99%) and the testability for clock networks. These key metrics also aid system designers in improving functional safety for mission-critical applications, such as automotive or industrial solutions.
Maestro CGMs are all digital, leading to a 10-15x area reduction over analog PLLs. These footprint reductions allow architects to instantiate multiple CGMs within a core block, driving true DVFS capabilities.
The generation modules are also fully synthesizable which improves the coverage area (up to 99%) and the testability for clock networks. These key metrics also aid system designers in improving functional safety for mission-critical applications, such as automotive or industrial solutions.
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