You are here:
Aeonic Generate Digital PLL for multi-instance, core logic clocking
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality digital PLL that enables distributed clocking for per-core dynamic frequency scaling (DFS) and fine-grained clock tuning. It reliably supplies a clock signal to processing elements across a wide frequency range, using standard cells and operating on core voltage (VDD) for simplified integration. In addition, the Aeonic Generate™ CGM supplies design teams with clock-specific telemetry that is read out through a standard interface for 3rd party silicon analytics platforms.
查看 Aeonic Generate Digital PLL for multi-instance, core logic clocking 详细介绍：
- 查看 Aeonic Generate Digital PLL for multi-instance, core logic clocking 完整数据手册
- 联系 Aeonic Generate Digital PLL for multi-instance, core logic clocking 供应商
PLL IP
- TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
- TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL
- TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
- TSMC GF Intel Samsung Integer-N Frequency Synthesizer PLL
- Jitter Cleaner PLL Digital Loop Filter
- TSMC Intel 32kHz Low-bandwidth Frequency Synthesizer PLL