The CL12481IP transmitter converts parallel 35bits (30bits of RGB data and 5bits of HSYNC, VSYNC, DE and Control1, Control2) of LVCMOS data into serial 5-LVDS data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a sixth LVDS link. The CL12481IP transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of LCD timing and control data (HSYNC, VSYNC, DE, Control1, Control2) are transmitted at a rate of 945Mbps per LVDS data channel. The CL12481IP transmitter is an ideal means to solve EMI and cable size problems associated with wide, high-speed CMOS interfaces.