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LVDS Transmitter 24(28)bit FPD-link 135MHz Single
The CL12463IP transmitter converts parallel 28bits (24bits of RGB data and 4bits of HSYNC, VSYNC, DE and Control) of LVCMOS parallel data into serial four LVDS data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. The CL12463IP transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 24bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, DE, Control1) are transmitted at a rate of 945Mbps per LVDS data channel. The CL12463IP transmitter is an ideal means to solve EMI and cable size problems associated with wide, high-speed CMOS interfaces.
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