You are here:
LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process
LVDS RX, UMC 40nm LP/RVT Low-K Logic process.
查看 LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process 详细介绍：
- 查看 LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process 完整数据手册
- 联系 LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process 供应商