LVDS Receiver
The LVDS_RX accept low voltage (±50 mV typical) differential input signals and translates them to 3.3V CMOS output levels. The receivers also support open, shorted, and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions
查看 LVDS Receiver 详细介绍:
- 查看 LVDS Receiver 完整数据手册
- 联系 LVDS Receiver 供应商
SERDES IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency