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LVDS Receiver 30(35)bit FPD-link 135MHz Single
The CL12482IP receiver converts serial five LVDS data streams data back into parallel 35bits (30bits of RGB data and 5bits of HSYNC, VSYNC, DE and Control1, Control2) of LVCMOS parallel. The CL12482IP receiver can be programmed for rising edge or falling edge clocks through a dedicated pin. The CL12482IP receiver is an ideal means to solve EMI and cable size problems associated with wide, high-speed CMOS interfaces.
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