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LVDS Receiver 24(28)bit FPD-link 135MHz Single
The CL12464IP receiver converts serial four LVDS data streams data back into parallel 28bits (24bits of RGB data and 4bits of HSYNC, VSYNC, DE and Control) of LVCMOS parallel. The CL12464IP receiver can be programmed for rising edge or falling edge clocks through a dedicated pin. The CL12464IP receiver is an ideal means to solve EMI and cable size problems associated with wide, high-speed CMOS interfaces.
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