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LVDS I/O Pad Set
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates up to 4.0 Gbps. The pad set includes a full complement of power, spacer, and adapter cells to assemble a complete pad ring by abutment. An included rail splitter allows isolated LVDS domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.
▪ 2.0 GHz LVDS Driver
▪ 2.0 GHz LVDS Receiver
▪ LVDS Voltage Reference
This 7nm library is available in a staggered flip chip implementation.
LVDS Specification Compliant:
• TIA/EIA-644-A - Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits
• IEEE Std 1596.3-1996
ESD Protection:
▪ JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
▪ JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C
▪ 2.0 GHz LVDS Driver
▪ 2.0 GHz LVDS Receiver
▪ LVDS Voltage Reference
This 7nm library is available in a staggered flip chip implementation.
LVDS Specification Compliant:
• TIA/EIA-644-A - Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits
• IEEE Std 1596.3-1996
ESD Protection:
▪ JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
▪ JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C
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LVDS IP
- TSMC GF LVDS Tx/Rx with optional CMOS I/O
- TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF