HEVC/AVC Single-core Video Encoder HW IP of Low-cost Version: 4K60fps
LVDS I/O Pad Set
▪ 2.0 GHz LVDS Driver
▪ 2.0 GHz LVDS Receiver
▪ LVDS Voltage Reference
This 7nm library is available in a staggered flip chip implementation.
LVDS Specification Compliant:
• TIA/EIA-644-A - Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits
• IEEE Std 1596.3-1996
ESD Protection:
▪ JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
▪ JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C
查看 LVDS I/O Pad Set 详细介绍:
- 查看 LVDS I/O Pad Set 完整数据手册
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LVDS IP
- Bi-Directional LVDS with LVCMOS
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane