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LPDDR5X/5/4X PHY in TSMC (N5, N4P, N3E, N3P, N3A)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package applications requiring high-performance LPDDR5X, LPDDR5, and LPDDR4X SDRAM interfaces operating at up to 8533 Mbps. With flexible configuration options, the LPDDR5X/5/4X PHY can be used in a variety
of mobile applications supporting LPDDR5X, LPDDR5 and/or LPDDR4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5X/5/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:
Single-ended Command/Address (C/A) and Data (DQ) signals
Differential signals (clock, data strobe, and WCK signals)
CMOS logic-level based C/A signals
of mobile applications supporting LPDDR5X, LPDDR5 and/or LPDDR4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5X/5/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:
Single-ended Command/Address (C/A) and Data (DQ) signals
Differential signals (clock, data strobe, and WCK signals)
CMOS logic-level based C/A signals
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