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LPDDR5 Secondary/Slave (memory side!) PHY
This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5 IP provides the unique opportunity to transmit data between a variety of devices such as AI coprocessors, in-memory compute solutions and emerging memory products.
This is a memory side (Slave-side) interface for AI processors and other ASICS seeking the latest high speed, low power LPDDR interface protocols for general purpose data transfer, while adhering to the well known and well defined LPDDR5 standard as specified by JEDEC.
This IP is designed for 7nm TSMC but can be ported to other logic processes. It is also suitable for a wide variety of memories such as DRAM, SRAM as well as emerging memories including non-volatile memories, with appropriate modifications.
This is a memory side (Slave-side) interface for AI processors and other ASICS seeking the latest high speed, low power LPDDR interface protocols for general purpose data transfer, while adhering to the well known and well defined LPDDR5 standard as specified by JEDEC.
This IP is designed for 7nm TSMC but can be ported to other logic processes. It is also suitable for a wide variety of memories such as DRAM, SRAM as well as emerging memories including non-volatile memories, with appropriate modifications.
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