LPDDR2 PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal LPDDR2 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC LPDDR2 SDRAM components in the market. The PHY components contain DDR specialized functional and utility I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. LPDDRn bus width can be from 4 bit to 72 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The combo PHY solution includes LPDDRn controller and PHY. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.

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