MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
LPDDR Controller ASIL B Compliant for LPDDR5/4/4X for Automotive Applications
The controller connects to the Synopsys LPDDR5/4/4X PHY or other LPDDR5/4/4X PHYs via the DFI 5.0 interface to create a complete memory interface solution. The Synopsys LPDDR5/4/4X Controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface.
The LPDDR controller block includes the advanced command scheduler, memory protocol handler, optional inline ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY. The Synopsys Controller seamlessly integrates with the Synopsys Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in
off-chip memory.
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LPDDR IP
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