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Low Voltage, Low Power Fractional-N PLLs
Perceptia’s DeepSub™ pPLL05 is a family of low power, low voltage all digital PLL featuring low-jitter and compact area. It is suitable for IoT and embedded clocking applications in systems running below the nominal core voltage at frequencies up to 1.5GHz. It is suitable as a clock source for moderate speed microprocessor blocks and other logic.
Perceptia’s second generation pPLL05 family is available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of technologies where it is silicon proven and can quickly port it to other technologies or foundries upon request.
To give IoT designers the maximum flexibility in managing power, pPLL05 is very small (< 0.01 sq mm) and low power (< 0.7mW in 22FDX). It is well suited to applications with a single low voltage power supply that the PLL shares with the blocks that use its output clock. Better jitter performance can be achieved if the pPLL05 has its own analog power supply.
pPLL05 integrates easily into any SoC design and includes all the views and models required by back end flows.
The pPLL05 is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL05 can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.
Perceptia’s second generation pPLL05 family is available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of technologies where it is silicon proven and can quickly port it to other technologies or foundries upon request.
To give IoT designers the maximum flexibility in managing power, pPLL05 is very small (< 0.01 sq mm) and low power (< 0.7mW in 22FDX). It is well suited to applications with a single low voltage power supply that the PLL shares with the blocks that use its output clock. Better jitter performance can be achieved if the pPLL05 has its own analog power supply.
pPLL05 integrates easily into any SoC design and includes all the views and models required by back end flows.
The pPLL05 is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL05 can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.
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Block Diagram of the Low Voltage, Low Power Fractional-N PLLs
