MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
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Low Power Wide Range PLL - GLOBALFOUNDRIES 65 65LPe
Analog Bits Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation. The PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC enviroents, such as high speed communication to low power consumer to memory interfaces.
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