MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
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Low Power RISCV CPU
特色
- RISC-V RV32 instruction set:
- I > full support
- M > partial support
- C > full support
- Machine mode only
- 32 vectorized interrupts
- Standard debug as defined per RISC-V
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