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Low power, high speed, and high density configurable Double Density SRAM
Novelics coolSRAM-1T embedded memory IP is the industry’s only siliconproven, single transistor SRAM IP solution that can be implemented in a bulk logic CMOS process without requiring additional masks or manufacturing steps. Use of coolSRAM-1T lowers overall system level cost and power consumption by reducing both the area of standard embedded SRAM and the number of external components.
Based on Novelics’ patented SRAM-1T technology, coolSRAM-1T is an ideal solution for high density SRAM integration in ASICs, ASSPs, VLSI and Systemon- Chip (SoC) applications. Embedded coolSRAM-1T blocks are custom configured by the designer and compiled to meet the design specifications, providing an unprecedented mix of low power and high density to minimize total system cost.
coolSRAM-1T IP requires only an unmodified standard logic CMOS process and therefore does not introduce additional manufacturing cost. Other single transistor SRAM offerings available on the market today require process modifications in the form of additional masks and additional manufacturing layers. These requirements can add up to 20% to the wafer cost and make other single transistor SRAM solutions not justifiable for a majority of the designs. Use of coolSRAM-1T IP even for a small amount of embedded memory can lower silicon cost significantly by reducing die size.
With the ability to reduce the die area by typically more than 25%, manufacturing yield can also be maximized. By incorporating coolSRAM-1T the design benefits from either a 50% increase in available logic area or 25% reduction in chip area for the typical SoC.
Based on Novelics’ patented SRAM-1T technology, coolSRAM-1T is an ideal solution for high density SRAM integration in ASICs, ASSPs, VLSI and Systemon- Chip (SoC) applications. Embedded coolSRAM-1T blocks are custom configured by the designer and compiled to meet the design specifications, providing an unprecedented mix of low power and high density to minimize total system cost.
coolSRAM-1T IP requires only an unmodified standard logic CMOS process and therefore does not introduce additional manufacturing cost. Other single transistor SRAM offerings available on the market today require process modifications in the form of additional masks and additional manufacturing layers. These requirements can add up to 20% to the wafer cost and make other single transistor SRAM solutions not justifiable for a majority of the designs. Use of coolSRAM-1T IP even for a small amount of embedded memory can lower silicon cost significantly by reducing die size.
With the ability to reduce the die area by typically more than 25%, manufacturing yield can also be maximized. By incorporating coolSRAM-1T the design benefits from either a 50% increase in available logic area or 25% reduction in chip area for the typical SoC.
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