1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
M31 Digital PLL IP in 6nm, 7nm, 12nm, 16nm, 22nm
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Digital PLL IP
- Ultra-Low Phase Noise Digital LC PLL
- Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
- Aeonic Generate™ AWM3 [PLL] actively responds to droop and enables DVFS with advanced clock health and droop telemetry
- 4-GHz Jitter-optimized low-power digital PLL
- 1.5-GHz Jitter-optimized low-power digital PLL
- 4-GHz Jitter-optimized low-power digital PLL