10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
Low-Power Bandgap Reference - Low Integrated Noise (62.5µVrms) in TSMC 40nm
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Block Diagram of the Low-Power Bandgap Reference - Low Integrated Noise (62.5µVrms) in TSMC 40nm
Power Management IP
- Power Management Subsystem
- SMIC 90nm Power Management Kit, 1.2v operating voltage
- SMIC 0.11um Power Management Kit,1.2v operating voltage
- SMIC 0.13um Power Management Kit,1.2v operating voltage
- HHGrace 0.11um Low Power Process 6track Power Management Kit
- HHGrace 0.11um ULL Process 6track Power Management Kit