NVM OTP in GF (180nm, 130nm, 65nm, 55nm, 40nm, 28nm, 22nm, 12nm)
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Low power AI accelerator
	For device makers, a small, inexpensive, low-power chip that can run the large AI models is needed to lead the market with their device features. A very efficient and low-cost, low-power way to achieve this is to compress large AI models and design a computer chip that runs such an AI compression algorithm. ABR has done exactly this with our patented AI time-series compression algorithm, called the Legendre Memory Unit (LMU).
 
The LMU was engineered by emulating the algorithm used by time-cells, a kind of neuron, in the human brain. The work was done by ABR in partnership with the neuroscience engineering research lab at U Waterloo where our company was spun out of.
 
		
The LMU was engineered by emulating the algorithm used by time-cells, a kind of neuron, in the human brain. The work was done by ABR in partnership with the neuroscience engineering research lab at U Waterloo where our company was spun out of.
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time series AI accelerator IP
- Edge AI Accelerator NNE 1.0
- Tensilica AI Boost
- AI Inference IP. Ultra-low power, tiny, std CMOS. ~ 100K parameter RNN
- Modern Audio DSP, designed for battery operated, high-performance, audio and voice applications
- MCU Platform for Industrial Applications
- 32-bit RISC-V processor specifically designed for the Automotive and Functional Safety markets






