ISP, Image Signal Processing, Real-time Pixel Processor for Automotive
Low-Latency IP 10G Ethernet MAC
INTERFACES:
On the Ethernet side, the MAC/SerDes interfaces directly to the optical module. No external PHY required.
On the internal user logic side, it has 3 interfaces. Two are FIFO interfaces. One FIFO interface is used for transmit purposes. The other is used for receiving purposes. A third interface is also available for direct data receiving, ultra low latency mode. This direct interface runs at 64 bit 156MHz Ethernet clock rate, offers the lowest possible latency. The FIFO interfaces runs at much higher frequency than the Ethernet clock rate.
Sustain full 10G line rate performance on both the receiving and transmitting side. Best performance even at smallest Ethernet packet size
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Ethernet MAC IP
- The Synopsys 1.6T Ethernet MAC IP is based on IEEE 802.3-2018 spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications
- Synopsys 1.6T Ethernet MAC IP
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
- 100G Ethernet MAC/RS
- 800G/400G/200G Ethernet MAC
- 40G/100G Ethernet PCS/MAC IP Cores