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Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks

High bandwidth PLL with accurately spaced 16-phase output clocks. Low Power/ Low Area hard macro with industry leading jitter performance for its power/area class.

Product is currently available in the following processes:
- TSMC - 28nm (HP, HPM, HPL, LP), 40nm (G, LP), 65nm (GP, LP), 90nm (G, LP), 130nm (G), 180nm
- Global Foundries - 40nm (G, LP), 65nm (GP, LP)
- IBM - 65nm (G, LP), 130nm, 180nm
- SMIC - 65LL, 90G, 110G, 130G
- ST - 90G

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PLL Clocking Jitter Phase Noise DDR multi-phase IP

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Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks

查看 Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks 详细介绍：

PLL Clocking Jitter Phase Noise DDR multi-phase IP

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添加产品

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