Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
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Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40
PMCC_PLL5GN40 is a PLL IP block which synthesizes low-jitter (<0.3ps RMS) 4.96GHz to 5.6GHz (5.28GHz typical) clock signals from the 620-700MHz reference clock. The pseudo-differential CMOS outputs are aligned to have ±35ps skew over PVT. The block is powered from the 0.9V (core) and 1.8V supply voltages. Silicon proven on 2 ASICs. Can be modified as per customer specifications.
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