The S3REG2516T40LP is a regulator circuit which has been designed to provide 0.90-2.8V with a load current of up to 25mA. The output voltage is programmable.
This S3REG2516T40LP features an automatic feedback sensing option to maintain a constant regulated output voltage level. It has been designed to provide a stable output in both low-drop and high-drop operation, while maintaining minimum ripple on supply lines in the presence of large load current spikes inherent with switching loads, e.g. high-speed ADCs.
The S3REG2516T40LP has been designed to allow low-drop operation (the PMOS pass device has been scaled for a voltage drop of 350mV). To achieve these goals, the voltage regulator requires a 4.7 F external ceramic capacitor.
The S3REG2516T40LP uses 2.5V thick oxide devices from a standard 40nm logic process. The circuit can be scaled for a range of load currents and the output voltage level is programmable.
- 40nm TSMC Logic LP Process, 6 Metals Used
- (No Analog Options) with Deep-Nwell
- 3.0V 3.6V Input Voltage
- 0.9V 2.8V 3% Output Voltage
- 25mA Load Current
- 350mV Drop Out Voltage
- Compact Die Area:
- Leakage Via Pass Device : 60nA
- Programmable Output Voltage
- Power Down Mode
- For maximum flexibility, the user can adjust the regulated
- output voltage if the S3REG2516T40LP is placed on a different
- The S3REG2516T40LP is readily portable to other
- manufacturing processes or can be customized for specific
- process option.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- General Purpose Low Drop Out Voltage Regulator
Block Diagram of the 来自于S3 Semi的TSMC 40nm通用LDO。