The S3REG1016T40LP is a regulator circuit which has been designed to provide 0.7-2.7V with a load current of up to 10mA. The output voltage is programmable.
The S3REG1016T40LP is a regulator circuit that features an automatic feedback sensing option to maintain a constant regulated output voltage level. It has been designed to provide a stable output in both low-drop and high-drop operation, while maintaining minimum ripple on supply lines in the presence of large load current spikes inherent with switching loads, e.g. high-speed ADCs.
The S3REG1016T40LP has been designed to allow low-drop operation (the PMOS pass device has been scaled for a voltage drop of 500mV). To achieve these goals, the S3REG1016T40LP requires a 1 F external ceramic capacitor.
The S3REG1016T40LP uses 2.5V thick oxide devices from a standard 40nm logic process. The circuit can be scaled for a range of load currents and the output voltage level is programmable.
- TSMC 40nm Logic LP Process, 7 Metals Used
- (No Analog Options) with Deep-Nwell
- 2.0V - 3.6V Input Voltage
- 0.7V - 2.7V 3% Output Voltage
- 10mA Load Current
- 500mV Drop Out Voltage
- Small Die Area
- Leakage Via Pass Device : 60nA
- Programmable Output Voltage
- Power Down Mode
- For maximum flexibility, the user can adjust the regulated output voltage if the S3REG10016T40LP is placed on a different chip.
- The S3REG10016T40LP is readily portable to other manufacturing processes or can be customised for specific customer requirements and it is designed with the Deep-Nwell process option.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog/VerilogA)
- Integration Support
- General Purpose Low Drop Out Voltage Regulator
Block Diagram of the 通用LDO，25mA/100mA输出电流，可编程输出电压。