MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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Low (Active) Power Memory
The low power embedded SP SRAM utilizes a different architecture than typical memory compilers and is designed to be used in SoCs that require low active power consumption. It uses foundry provided bit cell and complements industry’s commercially available embedded memory IP offerings to provide maximum flexibility for designers to meet power and performance goals.
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Low (Active) Power Memory IP
- Low (Leakage) Power Memory
- Single Port SRAM Compiler GF22FDX Low Power
- 1-Port Register File Compiler GF22FDX Low Power
- Low power, high speed, and high density configurable SRAM
- Low power, high speed, and high density configurable Double Density SRAM
- Low power, high speed, and high density Configurable ROM