Included at no additional charge with ISE™ Embedded, System Edition software
Xilinx provides AXI Exerciser IP which as AXI Master can generate AXI4 traffic for various modules/interconnect connected in system.
The Xilinx LogiCORE™ IP Advanced eXtensible Interface (AXI) exerciser is a core that stresses the AXI4 interconnect and other AXI4 peripherals in the system. It generates a wide variety of AXI4 transactions based on the core programming.
- AXI4 interface to program core for different traffic generation options
- Works as a master to issue read/write commands based on the programming sequence to CMDRAM
- Flexible data width capability (32-bit 64-bit) on Slave and Master AXI4 interface
- Interrupt pin indicating core completed generation of traffic
- Error interrupt pin indicating error occurred during core operation. Error registers can be read to understand the error occurred