Secure-IC's Securyzr™ High-performance AES-GCM accelerator - optional SCA protection
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Linearization of ADCs
Digital post‑linearization increases the effective resolution of analog‑to‑digital conversions. The linearization technology developed by SP Devices suppresses low order non‑linearities of high‑performance ADCs and non‑linearities caused by pre‑ADC analog components (such as amplifiers, filters and buffers).
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Linearization for ADCs IP
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 8x 9-bit, 1 GSPS ADCs, PLL
- Digital PreDistortion IP
- 14b 50Hz sensor ADC