Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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Linear regulator with ultra low quiescent current for retention applications
The qLR-Aubrey-ref-[1.9-4.4]-[1.2-3.3].01 is an ultra-low-quiescent-current regulator used to generate SoC internal supply for retention logic islets.
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Block Diagram of the Linear regulator with ultra low quiescent current for retention applications
LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL