The VPC-6 is a linear frame rate converter used to convert between frame rates while maintaining the appearance of smooth motion. Frame rate conversion by simply dropping or repeating frames has low complexity, but can result in severe motion judder. Motion compensated techniques can preserve fluidity, but are complex and expensive to implement. Using weighted contributions from adjacent video frames, the VPC-6 avoids motion judder associated with drop/repeat without the cost or complexity of motion compensation. When used in conjunction with the CXC-1 Configurable Cross Converter, the latter provides a complete system level wrapper including DRAM interface and seamless integration with other Crucial IP cores.
The VPC-6 is available with complete Verilog source code, Verilog test bench and bit-accurate C models as part of the license. Integration and programming guidelines are also included backed up by expert technical support.
A VPC-6 reference design is available for standard development kits from Xilinx and Altera for demonstration and evaluation purposes. The design includes a built-in user interface with embedded OSD to simplify access to key features of the IP. In addition to simplifying the evaluation of the VPC-6 IP core, the design also serves as a template for customer application development.