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LIN 2.2, 2.1 and 1.3 Protocol Controller IP
The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, LIN is slower, but thanks to its simplicity, is much more cost effective. Our Core is ideal for a communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as master or slave LIN node, depending on a work mode, determined by the microprocessor/microcontroller. Our controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes programmable timer, which allows to detect timeout and synchronization error. The DLIN is described at RTL level, empowering the target use in FPGA and ASIC technologies.
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Block Diagram of the LIN 2.2, 2.1 and 1.3 Protocol Controller IP
LIN Bus IP IP
- LIN Bus Controller – Basic and Safety-Enhanced
- LIN Bus Master/Slave Controller Core
- Local Interconnect Network (LIN) Soft Controller IP
- Configurable UART with FIFO, software and hardware flow control
- High Speed UART IP core - Universal Aysynchronous Receiver / Transmitter
- 8-bit FAST Microcontrollers Family