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Library of LVDS Ios cells in HLMC 28nm
This IP is a total solution for LVDS applications, including LVDS transmitter I/O, receiver I/O, common block and power/ground I/O. LVDS transmitter and receiver support 1.2Gbps maximum data-rate. LVDS transmitter I/O can obtain good impedance matching by setting internal terminal impedance enable. There are multi-bits controlling signals to get different differential output swings and common mode voltage.
LVDS receiver I/O can receive differential signals with full-scale common voltage and small differential voltage.
LVDS receiver I/O can receive differential signals with full-scale common voltage and small differential voltage.
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LVDS IP
- TSMC GF LVDS Tx/Rx with optional CMOS I/O
- TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF