The 10GBase-KR Core attaches directly to our 10GBase-R Medium Access Controller and Physical Coding Sublayer Core. It provides 10Gb/s FEC-protected transmission using Xilinx Series 7 FPGAs.
The best-in-class true 16-bit SDR datapaths and interfaces clocked at 625 MHz feature the lowest area currently available on FPGAs. That is 3000 LUTs and 3300 FF including FEC, AN and GTH interface! Verified and tested!
* 16 bit UDP/IP framer
* 16 bit TCP/IP framer
* 32 bit interface adapter for simple connection to 3rd -party upper-layer cores.
- 16 bit datapaths and user interfaces (TX/RX) @ 625 MHz
- Implements clause 73: Auto-Negotiation for backplane and copper cable assembly
- Implements clause 74: Forward Error Correction (FEC) sublayer for BASE-R PHYs
- Implements the GTH-interface
- + lowest resource utilization!
- Design Files: Verilog and SystemVerilog
- Example Design: Verilog and SystemVerilog
- Test Bench: SystemVerilog
- Constraints File: XDC and TCL placement
- Simulation: SystemVerilog
- Design Entry: Vivado 2015.1
- Simulation: ModelSim 10.3D
- Synthesis: Vivado 2015.1
- 10G Ethernet (10GBase-KR)