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Least-Area 10GBase-KR Ethernet FEC/AN Core
The 10GBase-KR Core attaches directly to our 10GBase-R Medium Access Controller and Physical Coding Sublayer Core. It provides 10Gb/s FEC-protected transmission using Xilinx Series 7 FPGAs.
The best-in-class true 16-bit SDR datapaths and interfaces clocked at 625 MHz feature the lowest area currently available on FPGAs. That is 3000 LUTs and 3300 FF including FEC, AN and GTH interface! Verified and tested!
Optionally available:
* 16 bit UDP/IP framer
* 16 bit TCP/IP framer
* 32 bit interface adapter for simple connection to 3rd -party upper-layer cores.
The best-in-class true 16-bit SDR datapaths and interfaces clocked at 625 MHz feature the lowest area currently available on FPGAs. That is 3000 LUTs and 3300 FF including FEC, AN and GTH interface! Verified and tested!
Optionally available:
* 16 bit UDP/IP framer
* 16 bit TCP/IP framer
* 32 bit interface adapter for simple connection to 3rd -party upper-layer cores.
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