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Key Expander Core
The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P and AES-GCM cores. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.
Two architectural versions are available to suit system requirements. The Standard version is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block.
The KEXP core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
Two architectural versions are available to suit system requirements. The Standard version is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block.
The KEXP core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
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Block Diagram of the Key Expander Core
