JESD207 RFIC IP

特色

• Implemented in Unencrypted Verilog, VHDL and SystemC
• Follows JTAG basic specification as defined in JTAG Specification 3.
• Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6.
• Supports all the JTAG tap instructions.
• Supports programmable clock frequency of operation.
• Checks for following
• -> Check-points include Initialization rules,
• -> State based rules,Active Command rules,
• -> Read/Write to Instruction and data register Rules.
• Supports Instruction register and data register of size up to 64 bits.
• Proficiency to extend with user defined instructions and registers.
• Has ability to read BSDL file and
• -> Automatically generate testvectors to test all BSDL cell types
• -> Automatically generate SVA assertions properties
• Supports constraints Randomization.
• Status counters for various events on bus.
• Support all types of timing and protocol violation detection.

优势

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

可交付内容

• The JESD207 RFIC interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases.
• Lint, CDC, Synthesis, Simulation Scripts with waiver files.
• IP-XACT RDL generated address map.
• Firmware code and Linux driver package.
• Documentation contains User s Guide and Release notes.

• 查看 JESD207 RFIC IP 完整数据手册
• 联系 JESD207 RFIC IP 供应商